The impact of open-source EDA / VLSI technologies to the semiconductor ecosystem
Moderator : David Atienza ( EPFL )
Open-Source Hardware and EDA Tools Must Be as Open-Software
Abstract: The talk will describe the approach at Good to develop a complete roadmap and ecosystem for open-source technologies. The main aspects to consider is that fundamentally there is no difference between hardware and software regarding open-source technologies, and this approach has worked very well for the software engineering community. Therefore, it should be adopted as soon as possible and in a consistent way by all hardware vendors.
BIO: Tim 'mithro' Ansell is a software engineer at Google and has been developing open source software for 20+ years. Tim has recently started trying to shake things up in the hardware accelerator development ecosystem by removing roadblocks to having a completely open ecosystem. Recently he worked with SkyWater Foundry to release a fully open source, manufacturable PDK for their 130nm process node and is funding a free shuttle program for open source designs. He has also contributed to projects in the open EDA ecosystem like OpenROAD, OpenRAM, Magic and many others.
Open Source HW IP - Barriers to Adoption for High Volume Production
Abstract : The talk will describe barriers to adoption of open-source IP and opportunities to overcome these barriers. We will provide a brief overview of the RISC-V instruction set architecture and describe the CORE-V family of open-source cores that implement the RISC-V ISA. RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC- V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. Based on the original PULP Platform development at ETH Zurich, CORE-V is a series of RISC-V based open-source processor cores with associated processor subsystem IP, tools and software for electronic system designers. The CORE-V family provides quality open source IP in line with industry best practices in both silicon and FPGA optimized implementations. These cores can be used to facilitate rapid design innovation and ensure effective manufacturability of production SoCs.
BIO: Rick O'Connor is Founder and serves as President & CEO of the OpenHW Group a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate on open source cores, related IP, tools and software projects. The OpenHW Group is leading the industry wide adoption of commercial quality open-source HW IP such as the Core-V Family of RISC-V based open-source cores with associated processor subsystem IP, tools and software.
Previously Rick was Executive Director of the RISC-V Foundation. RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded by Rick in 2015 with the support of over 40 Founding Members, the RISC-V Foundation currently comprises more than 235 members building an open, collaborative community of software and hardware innovators powering processor innovation. Born in academia and research, the RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
Recent Developments in DARPA-Funded Open-Source Chip Design
Abstract: Focusing on the portfolio of DARPA Program Manager Serge Leef, who oversees nearly two dozen open-source academic and commercial U.S. government-funded microelectronics research efforts, this talk will offer insight into ongoing DARPA-funded open-source chip design programs and touch on the future directions of open-source EDA tools. Projects to be discussed span from fully open EDA software flows to ASIC verification tools and libraries of silicon-proven open-source IP blocks.
Bio: Julian Warchall is a Lead Engineer at Booz Allen Hamilton where he provides consulting in microelectronics to U.S. government clients including the Defense Advanced Research Projects Agency (DARPA), Air Force Research Labs, and Naval Surface Warfare Center. Julian received the B.S. degree in electrical and computer engineering from the University of Virginia, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, San Diego, where he designed novel integrated circuits for low power signal acquisition in medical applications.
From Open Source to Commercial Products - It’s about time.
Abstract : For the first time in the history of the semiconductor industry it is possible to design, verify, manufacture Systems-on-Chip (SoC)’s that have been completely developed using an open source process technology, open source IP and open source design automation environment.
In a collaborative effort with Google and SkyWater, efabless' team has designed and implemented the striVe SoC family using SkyWater’s SKY130 130nm process, efabless’ OpenLANE RTL2GDS no-human-in-the-loop SoC compiler and several key FOSS components including standard cell and IO libraries from SkyWater and OSU, Dual port SRAM created using OpenRAM, PicoRV32 RISC-V CPU and future versions that will include open source eFPGA blocks - all of them are available under the Apache 2.0 license.
Bio : Mohamed Kassem is the co-founder and CTO of efabless.com. The company offers a cloud-based platform that gives chip designers worldwide instant access to silicon-proven IP, foundry PDK, complete EDA tool chain and access to customers through a rich marketplace without pre-tape-out cost and without an NDA. Prior to launching efabless in 2014, Mohamed held several technical and global leadership positions within Texas Instruments’ Wireless Business Unit. He joined TI in 2000 at the beginning of the digital telephony revolution fueled by mixed signal integration of major phone functions on a single SoC. He led the development of first low power mixed-signal design in 45nm, 28nm for mobile applications processors.